There is a trend in the market for ASIC devices that are becoming more and more power-sensitive. As the geometries are becoming ever smaller, ASIC devices having more than 500 K gates are becoming the norm. Furthermore, there is a trend that the ASIC devices are incorporating ever more logic functions. Additionally, the frequencies of operation for such ASIC devices are also increasing. This, in turn, results in ASIC devices that consume more and more power. For such ASIC devices in the area of laptop computing and wireless communication as well as in many consumer products, the biggest cost factor nowadays is power consumption. Therefore, new designs of ASIC devices have to be developed in order to save power.
One way to save power is to turn off sections of the logic circuitry that are not active, and to allow the sections of the circuitry to be active only when needed. Among others, power can be saved by putting logic circuitry to a "sleep" mode with an interrupting mechanism to "wake up" the logic circuitry when needed or to run the different domains of the ASIC device with as slow clock frequencies as possible. The last mentioned possibility poses, however, the problem that the various clock signals having different frequencies have to be synchronized and such a synchronization is impaired by the skew effect which comes about because of the difference in time that the clock signals need to reach the flip flop which is nearest to the clock driver as compared to the time needed for the clock signals to arrive at the flip flop which is most distant from the clock driver.
As can be seen from the above, the distribution of clock signals is getting ever more important with increasing integration density and increasing clock rates in complex ASIC devices. Therefore, clock schemes, such as the single ended driver scheme, the double ended driver scheme, the local buffering scheme and the H-tree scheme, have been developed to assure, within a particular chip, that the skew on the clock signal lines does not exceed a maximum value which depends on the particular technology used.
The clock line network is the most critical network as concerns the design of the ASIC device. The fanout and the capacitive load related thereto is higher by two or three orders of magnitude as compared to such values in usual signal networks. Furthermore, the clock signal network extends generally across the hole surface of the chip, and the skew produced mainly by RC delays, has the effect that the clock signal is not synchronously provided at all the circuits which need the clock signal.
One has tried to solve the problem of the skew by providing an on-chip PLL circuit in the ASIC device itself to synchronize the various clock signals. In other words, in the prior art, each derived clock signal was generated asynchronously, and synchronization stages have been used to transfer the clock signals from one clock domain to another domain. However, this solution adds to the complexity of the ASIC device itself. Furthermore, the prior art solution is costly in terms of logic required and is not working in all the applications.